Modern microprocessors employ large on-chip random access memories (RAMs) in a variety of ways to enhance performance. These RAMs are typically static (SRAMs) due to associated speed advantages. The most common usage is in the form of on-chip caches. In many instances, such RAMs constitute the majority of transistors consumed on chip and are the largest occupants of chip area.
Embedded RAMs give rise to two particular problems during chip manufacturing. Because an embedded RAM occupies a significant portion of a chip's area, the probability that a defect lies within the RAM is relatively high. The RAM thus becomes a controlling factor in chip yield. Second, the embedding of RAM not only makes its own testing difficult, but also impairs testability of all other functions on chip, such as the core logic. For example, much of the testing of other functions requires the use of the embedded RAM, which must function properly.
Traditionally, semiconductor manufacturers have tackled RAM yield problems by incorporating a repair scheme with redundant rows and/or columns. For embedded RAM, however, this compounds the testing problems because a diagnosis to identify defects and the repair of those defects are required before the testing of core logic, for example, can begin.
Built-in Self-Test (BiST or BIST) and Built-in Self-Repair (BiSR or BISR) have been implemented as a solution to both of the above problems. Conventional solutions include both “soft” and “hard” repair solutions. A “soft” repair solution is based in software and must be performed each time the integrated circuit is powered-up. A “hard” repair solution is performed once and is available upon applying power to the integrated circuit.
Self-repairing memory elements are described in U.S. Pat. No. 6,697,290 and U.S. Pat. No. 6,914,833. Embedded circuitry is used to test the memory element. Each self-repairing memory element includes a number of bits represented by circuit elements referred to as a bit slice as well as a redundant bit slice. A bit slice includes an array, a sense amplifier and an input/output (I/O) block. When the array of bit slices forming a memory element does not include a defect, as indicated by a pass condition, the redundant bit slice is not used. When a defect is encountered, data flow is routed around the bit slice containing the defect and the redundant bit slice is used in its place. Any and all defects occurring in the same bit slice can be repaired as a repair occurs as the result of a rerouting or remapping of bit slices such that the defect or defects are bypassed.
Integrated circuits with embedded memory elements with “hard” repair capability may use an eFuse module electrically coupled to the memory elements. The eFuse module contains one-time programmable fuse-like elements that can be used to store information. One application of this technology is to provide circuit performance tuning. If certain sub-systems fail, are taking too long to respond, or are consuming too much power, the integrated circuit can change configuration behavior by “blowing,” that is, opening a fuse within a programmable eFuse circuit. When an eFuse module is used to store repair information, some embodiments include additional control logic for programming and loading the repair information into the memory elements. The repair information is loaded into the memory elements from the eFuse module shortly after integrated circuit power up.
These conventional solutions use top-level routing resources to integrate multiple circuits for communicating with test and embedded memory interfaces. These conventional solutions often restrict the placement and grouping of embedded memory circuits based on memory size, performance and type. In addition to the above restrictions, the conventional solutions require significant modification to the embedded memory circuits and significant processing time as each individual memory group is issued a request from the test interface before information is communicated from a particular embedded memory to the test interface.